The present invention relates to a word line driving circuit, a semiconductor memory device including the same, and a method for testing the semiconductor memory device, and more particularly to an apparatus and a method adapted to facilitate detecting whether a word line fails or not in a semiconductor memory device.
As it is well known, a word line controls a gate of a memory cell in a semiconductor memory device. A conventional word line driving circuit will be described below.
FIG. 1 illustrates a schematic circuit diagram of a conventional word line driving circuit.
Specifically, FIG. 1 illustrates a word line driving circuit for controlling a word line provided with a main word line and a sub word line. Currently, the word line has a hierarchical structure of a main word line MWL and a sub word line SWL, in which the sub word line SWL controls a gate of a memory cell.
As shown in FIG. 1, the conventional word line driving circuit includes a phi X driver 110 and a sub word line driver 120. The phi X driver 110 outputs a phi X control signal PX_J having address information. The sub word line driver 120 drive a sub word line in response to a main word line signal MWLB_I and the phi X control signal PX_J.
Here, a signal PXB_J, which is generated by decoding row address information, selects a sub word line. The signal MWLB_I refers to a main word line signal. In addition, the signal SWL_K, which is a resultant output of the word line driving circuit, refers to a signal for driving a word line. In this driving scheme, the signal SWL_K refers to a signal for driving the sub word line because the sub word line directly controls a memory cell.
As for the operation of the conventional word line driving circuit, the signals MWLB and PXB are at logic high levels in a state that a word line is not activated, i.e., in a precharge mode. At this time, transistors MP0 and MP1 are turned off and transistors MN0, MN1 and MN2 are is turned on, whereby the word line SWL maintains its logic low state.
When an active command is applied from the outside, the signals MWLB and PXB go to logic low levels after a predetermined time in synchronization with an inputted address. The phi X control signal PX goes to a logic high level because it is an inverted signal of the signal PXB. At this state, the transistors MP0 and MP1 are turned on but the transistors MN0, MN1 and MN2 are turned off, thus enabling the word line SWL to a logic high state.
Though FIG. 1 is a simple circuit diagram illustrating the operation of the conventional word line driving circuit, an actual memory device has a more complicated structure for driving a word line. However, this complicated actual structure is not necessary in describing the background of the present invention so that further description for it will be omitted herein.
FIG. 2 is a block diagram illustrating the arrangement of the word line driving circuit of FIG. 1 in a cell array of a conventional memory device.
FIG. 2 illustrates a main word line MWLB, a plurality of sub word lines SWL branched from the main word line MWL, sub word line drivers SWD for driving the sub word lines SWL, and connections of a plurality of the phi X control signal PXB thereamong. This configuration is a typical one and it can be easily appreciated by a person of ordinary skill in the art, so that further detailed description will be omitted herein.
FIG. 3 is a circuit diagram illustrating how sub word lines are allocated to a main word line in a conventional semiconductor memory device. Referring to FIG. 3, sub word lines SWL0, SWL2, SWL4 and SWL6 are allocated to a main word line MWLB0, and sub word line drivers are also allocated to the sub word lines.
With the increasing demands for high capacity semiconductor memory devices, semiconductor devices have shrunk in size so as to highly integrate more and more memory cells within a small chip area. As the semiconductor devices shrink in size, a bridge fail between interconnections frequently may occur in a highly dense area of a core region of a memory cell.
If the bridge between the interconnections serves as a low-resistance resistor, i.e., in a weak fail, there is no problem in a normal operation but may cause the memory device to be deteriorated with the elapse of a predetermined use time or after a device has undergone a burn-in test. In particular, there may be a number of weak bridge fails between adjacent lines such as word lines which are used as an interconnection as well as gate material for a memory cell.
However, the conventional memory device does not have an apparatus or a device adapted to detect the bridge fail of the word line yet.